1. Field of the Invention
The present invention relates to clock synchronizing circuits and, more particularly, to a digital delay locked loop circuit for synchronizing an internal clock to an external system clock in a synchronous semiconductor memory device.
The present application is based on Korean Application No. 59445/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Conventionally, a synchronous semiconductor memory device includes an external system clock signal CLK and a clock buffer circuit for generating internal clock signal PCLK. Internal clock PCLK is supplied to each circuit of the semiconductor memory device. The clock buffer circuit simply buffers external system clock CLK to produce internal clock PCLK. Inevitably, a phase difference between external system clock CLK and internal clock PCLK is created.
The phase difference between external system clock CLK and internal clock PCLK results in a corresponding response delay in the semiconductor memory device. Accordingly, a need remains for a semiconductor memory device having an internal clock synchronized with an external system clock CLK to thereby eliminate undue delay.
A variety of approaches have been taken to solve this problem. One approach developed to minimize the phase difference between external system clock CLK and internal clock PCLK involves using a phase locked loop (PLL) circuit. A second approach involves using a delay locked loop (DLL) circuit.
The operation of a PLL synchronizing circuit will be explained below with reference to FIG. 1. The PLL circuit shown in FIG. 1 comprises a phase detector 12, a loop filter 14, and a voltage controlled oscillator 16. When external system clock CLK and internal clock PCLK are applied to phase detector 12, it detects the phase difference and supplies a phase difference detection signal to loop filter 14. Loop filter 14 is a low-pass filter which generates a direct current control voltage V(t) by filtering the phase difference detection signal. Loop filter 14 supplies control voltage V(t) to voltage controlled oscillator 16 connected, in turn, to the output port. Voltage controlled oscillator 16 generates internal clock PCLK having a frequency corresponding to the level of control voltage V(t) output from loop filter 14.
Consequently, if the phase difference between external system clock CLK and internal clock PCLK has a positive value, control voltage V(t) is increased. By doing so, the cycle of internal clock PCLK output from voltage controlled oscillator 16 is reduced, and thus the phase difference between external system clock CLK and internal clock PCLK is reduced. On the other hand, if the phase difference between the external clock CLK and internal clock PCLK has a negative value, control voltage V(t) is decreased resulting in an increase in the cycle of internal clock PCLK output from voltage controlled oscillator 16 and a decrease in the phase difference between external system clock CLK and internal clock PCLK.
The operation of a DLL synchronizing circuit is similar to that described above. In the case of a DLL circuit, voltage controlled oscillator 16 is replaced by a voltage controlled delay circuit. The delay produced by the voltage controlled delay circuit varies according to control voltage V(t).
PLL and DLL synchronizing circuits have several disadvantages. The locking time, i.e., the time required to synchronize the internal clock PCLK with the external system clock CLK, is long. Increased locking time results in increased data access time, and thus, slower acquisition times. Additionally, the synchronizing circuit must be operated at all times and during all device states, including standby, increasing the standby current and the consequent power consumption.